An insulated-gate field-effect transistor, such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying channel extending between source and drain regions in the semiconductor substrate. Typically, the substrate is divided into a plurality of active regions through an isolation process, such as field oxidation or shallow trench isolation. A thin oxide layer is grown on an upper surface of the semiconductor substrate in the active regions. This thin oxide layer serves as the gate dielectric for subsequently formed transistors. A plurality of polysilicon gates are formed, and dopants are implanted to define the source/drain regions.
As transistor channels shrink below 0.5 microns, the limitations of conventional transistor processing become more apparent. To reduce short channel effects and operating voltage in deep sub-micron transistors, the depth of the source/drain junctions and the thickness of the gate oxides are desirably reduced. Devices become more susceptible, however, to diffusion of electrically active impurities located in the gate across the gate oxide and into the active area of the transistor as the gate oxide thickness decreases below 50 angstroms.
The presence of these impurities within the channel region can undesirably alter the threshold voltage of the device. This problem is especially acute for boron implanted gates. For example, when forming a P-channel MOS transistor, boron is typically implanted into the polysilicon gate. Such implanted boron may diffuse through a thin gate oxide into the underlying channel and silicon substrate and adversely affect device performance.
A number of techniques have been developed to attempt to reduce diffusion of dopants, especially boron, into the gate oxide and into the underlying channel. For example, U.S. Pat. No. 5,650,344 to Ito et al. discloses a polysilicon gate separated by a re-oxidized nitrided oxide film. The nitrided region underlying the gate oxide retards the diffusion of boron from the boron doped polysilicon gate into the silicon substrate. U.S. Pat. No. 5,879,975 to Karlsson et al. discloses nitrogen implantation at high levels into the gate to prevent subsequent impurity penetration through the gate oxide.
Other similar methods are disclosed by U.S. Pat. No. 5,885,877 to Gardner et al., wherein a nitride diffusion retarding barrier layer is disposed at the bottom of the gate to reduce dopant which diffuses into the gate oxide from the gate. In particular, a lower gate layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate oxide disposed therebelow, and an upper gate layer is formed on the lower nitrogen layer and is doped to form a highly conductive layer. Together, the upper and lower gate layers form a composite gate electrode which incorporates a diffusion-retarding barrier adjacent to the underlying gate dielectric.
U.S. Pat. No. 5,891,809 to Chau et al. discloses a method for forming a very thin nitrided oxide layer. First, a substrate is oxidized in a chlorinated dry oxidation followed by a low temperature pyrogenic steam oxidation. Next, a low temperature anneal is performed, followed by a high temperature anneal in an inert ambient.
An article titled "Improvement of Gate Dielectric Reliability for p+Poly MOS Devices Using Remote PECVD Top Nitride Deposition on Thin Gate Oxides" by Wu et al. discloses a dual layer dielectric formed by remote plasma enhanced chemical vapor deposition (RPECVD) of an ultra-thin stoichiometric nitride onto a thin oxide thermally grown on an n-type silicon substrate. A 0.8 nm layer of plasma nitride blocks boron atom diffusion from a heavily implanted p+ polysilicon gate electrode under conditions of an aggressive implant activation anneal.
A thermally grown oxide is typically formed by exposing the silicon substrate surface to an oxygen containing ambient. In a wet oxidation process, steam is included in the ambient. The oxygen causes the silicon surface to be partially consumed and converted into the oxide. A rate of growth of the oxide depends on a number of factors, and, unfortunately, irregularities and defects occur in the oxide. Such irregularities may be caused by irregularities in the silicon surface and/or from the oxide itself. So called "interface trap sites" may be formed at the oxide/silicon interface which severely limits the device electrical performance. Post oxidation anneal reduces these interface trap sites, and consequently, an interface trap site density associated therewith. As discussed above, nitrogen is incorporated into the oxide layer to suppress boron penetration. Unfortunately, nitrogen is opaque to oxygen, and the interface trap sites can not be completely reduced or eliminated during the anneal.
Furthermore, thinner gate oxides also increase concerns about hot carrier damage, higher leakage current and oxide breakdown due, in part, to increased electrical fields across the gate oxide. In addition to reliability concerns, thin gate oxides present significant manufacturing challenges as well, particularly with respect to providing a uniform nitride thickness that can be produced repeatedly in a manufacturing environment.
Despite the problems noted, thin gate oxides are desirable because the transistor drive current is inversely proportional to the gate oxide thickness over a wide range of operating conditions. Since higher drive currents result in faster devices, a great deal of effort has been directed towards reducing the gate oxide thickness without significantly reducing the reliability of the integrated circuit.